- 9月 21 週一 200910:53
寬字元
- 9月 15 週二 200912:21
Porting
- 3月 23 週一 200921:10
Approximate String Matching
- 3月 23 週一 200921:08
Edit Distance
- 11月 18 週二 200820:39
CSMA/CA
http://en.wikipedia.org/wiki/CSMA/CA
In computer networking, CSMA/CA belongs to a class of protocols called multiple access methods. CSMA/CA stands for: Carrier Sense Multiple AccessCollision Avoidance.
In CSMA, a station wishing to transmit has to first listen to the
channel for a predetermined amount of time so as to check for any
activity on the channel. If the channel is sensed "idle" then the
station is permitted to transmit. If the channel is sensed as "busy"
the station has to defer its transmission. This is the essence of both
CSMA/CA and CSMA/CD. In CSMA/CA (LocalTalk), once the channel is clear,
a station sends a signal telling all other stations not to transmit,
and then sends its packet. In Ethernet 802.3, the station continues to
wait for a time, and checks to see if the channel is still free. If it
is free, the station transmits, and waits for an acknowledgment signal
that the packet was received.
In computer networking, CSMA/CA belongs to a class of protocols called multiple access methods. CSMA/CA stands for: Carrier Sense Multiple AccessCollision Avoidance.
In CSMA, a station wishing to transmit has to first listen to the
channel for a predetermined amount of time so as to check for any
activity on the channel. If the channel is sensed "idle" then the
station is permitted to transmit. If the channel is sensed as "busy"
the station has to defer its transmission. This is the essence of both
CSMA/CA and CSMA/CD. In CSMA/CA (LocalTalk), once the channel is clear,
a station sends a signal telling all other stations not to transmit,
and then sends its packet. In Ethernet 802.3, the station continues to
wait for a time, and checks to see if the channel is still free. If it
is free, the station transmits, and waits for an acknowledgment signal
that the packet was received.
- 11月 16 週日 200816:49
SystemC
http://en.wikipedia.org/wiki/SystemC
SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power during transaction-level modeling , behavioral modeling, and High Level Synthesis. SystemC is a set of library routines and macros implemented in C++, which makes it possible to simulate concurrent processes, each described by ordinary C++ syntax. Instantiated in the SystemC framework, the objects described in this manner may communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined.
SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power during transaction-level modeling , behavioral modeling, and High Level Synthesis. SystemC is a set of library routines and macros implemented in C++, which makes it possible to simulate concurrent processes, each described by ordinary C++ syntax. Instantiated in the SystemC framework, the objects described in this manner may communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined.
- 11月 15 週六 200817:27
Fault Injection
http://en.wikipedia.org/wiki/Fault_injection
In software testing, fault injection is a technique for improving the coverage of a test by introducing faults in order to test code paths, in particular error handling code paths, that might otherwise rarely be followed. It is often used with stress testing and is widely considered to be an important part of developing robust software[1].
In software testing, fault injection is a technique for improving the coverage of a test by introducing faults in order to test code paths, in particular error handling code paths, that might otherwise rarely be followed. It is often used with stress testing and is widely considered to be an important part of developing robust software[1].
- 11月 15 週六 200814:32
Fault Model
http://en.wikipedia.org/wiki/Fault_model
A fault model is an engineering model of something that could go
wrong in the construction or operation of a piece of equipment. From
the model, the designer or user can then predict the consequences of
this particular fault. Fault models can be used in almost all branches
of engineering.
A fault model is an engineering model of something that could go
wrong in the construction or operation of a piece of equipment. From
the model, the designer or user can then predict the consequences of
this particular fault. Fault models can be used in almost all branches
of engineering.
研究成果 (1)